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- memory cell diagram 存储单元图
- A transistor memory cell can be made with any number of terminals. 晶体管存贮单元端点的数量是不受限制的。
- English: Complete neuron cell diagram with Simplified Chinese captions. 中文(简体)?:神经元细胞结构简体中文示意图。
- English: Complete neuron cell diagram with Traditional Chinese captions. 中文(繁体)?:神经元细胞结构繁体中文示意图。
- Description English: Complete neuron cell diagram with Traditional Chinese captions. 中文(繁体):神经元细胞结构繁体中文示意图。
- Characterize standard logic cells and memory cells. 提取标准逻辑单元和存储电路的参数。
- The memory cells may be multistate memory cells. 该存储单元可以是多状态存储单元。
- Description English: Complete neuron cell diagram with Simplified Chinese captions. 中文(简体):神经元细胞结构简体中文示意图。
- This problem can occur if 70 (binary 1000110) has been changed to 6 (binary 000110) by an unstable memory cell. 如果不稳定的内存单元已将70(二进制为1000110)更改为6(二进制为000110),则会发生此问题。
- The generation mechanism of stress induced leakage current( SILC) in flash memory cell is studied by experiments. 通过实验研究了闪速存储器存储单元中应力诱生漏电流(ILC)产生机理.
- The use of the program in 8237 will realize the magic memory modules of the data copied to several other memory cell. 在该程序中利用8237实现了将内存中魔几个单元的数据复制到另外几个存储单元。
- US Patern No. 5834806, 1998, “Raised-Bitline, Contactless, Trenched, Flash Memory Cell”, by R.L. Lin, C.H.-H Hsu, M.S. Liang. “极快速拟动态非挥发性快闪记忆体之阵列结构与其执行编码时临界电压自我校正方法”;林瑞霖;徐清祥.
- The mirror image position plan through saves each bit memory in an insulation grid both sides method in each memory cell two bits. 镜像位方案通过把每个比特存储在一个绝缘栅两端的方法在每个存储单元中存储两个比特。
- One of the main difficulties of quantum computation is that decoherence destroys the information in a quantum computer memory cell. 量子计算机存储单元的相干脱散，破坏量子态中的信息，是量子计算机难以实现的主要原因之一。
- Reading the charges stored on the floating gate of a memory cell is one of the most critical operations in an EEPROM device. 设计者常常要在灵敏放大器的面积、功耗以及读数据的速度之间折衷考虑。
- Physical addresses are used to address memory cells in memory chips. 物理地址是用来真正访问内存单元的地址。
- Unused memory cells following the BELL&RET command are considered free. 在电铃&浸水使柔软指令之后的不用记忆单元是考虑过的免费。
- Flip-flops are a key componemt and memory cells of sequential logic circuit. 触发器是构成时序逻辑电路的存储单元和核心部件。
- Meanwhile the relation of SNM and the gate width is also analyzed, which is consistent with the experiment. The design rules of VDSM SRAM memory cell are given. 文中同时分析了栅宽与 SNM的关系 ,其结论与实验结果一致 ,并给出了 VDSM SRAM存储单元设计中应注意的问题
- Based on the unified ferroelectric device model which is applied practically to the design, the 2T 2C configuration of the ferroelectric DRO memory cell is discussed in detail. 基于被应用于实际设计之中的统一的铁电器件模型，详细讨论了2T?2C组态的铁电破坏性读出存储器单元的设计。
