您要查找的是不是:
- Low Power Logic Circuits Design and Application in Risc Design 低功耗逻辑电路设计及在RISC设计中的研究
- medium power logic gate 中功率逻辑门
- Lesson1 How does a logic gate in a microchip work? 第一课芯片上的逻辑门是如何工作的?
- low power logic 低功率逻辑
- Inspiratory capacity and low power consumption. 吸气量大、功耗低。
- Keywords: Low power testing, BIST. 关键词:低功率测试、自我测试技术。
- A structure of TLB for low power is introduced. 介绍了一种低功耗TLB结构。
- Fast data transmission and low power consumption. 传输数据速度快,功耗底。
- Here are some nerve cells, seen in low power. 低倍镜观察神经元细胞。
- An improved Low Power Booth Encoder is proposed. 编码是快速乘法运算的基础;
- Low power precision wirewound fixed resistors. 英文名: Components for electronic equipment.
- Literal Logic Gate, ternary invertor has been explained by this quenching concept. 主要从事化合物半导体器件及其集成电路、单片及混合光电集成电路的研究工作。
- To obtain high performance and low power device, gate oxide thickness shrinkage is a main stream in modern ULSI industry. 摘要:为了达到高性能和低电压之元件,减少闸极氧化层厚度是现代超大型积体电路工业的一个主流。
- SSI chips are usually basic logic gates and flip-flops. 小型集成电路通常是最基本的逻辑栅门。
- High integration of imported large scale gate array device and high-speed CMOS integrated circuits ensure product reliability and low power consumption. 采用高速CMOS集成电路,进口超大规模门阵列器件,集成化高,保证了产品的可靠性和低功耗。
- After study a series array multipliers algorithms and architectures, . the author design a high-performance multiplier in logic gate level, which using Booth and Wallace skill. 本文研究讨论了各种不同阵列乘法器的结构和原理,并完成了在门电路级设计了32位基4Booth编码并采用42压缩的Wallace高性能阵列乘法器电路。
- A low power AMBA bus system is implemented. In order to separate the core logic from bus interface, a new local bus is defined. 完成了低功耗的AMBA总线系统的设计,并在总线接口和核心逻辑分离的指导原则下,定义了一种新的局部总线。
- Once this occurs, even though the ions may be widely separated, the manipulation of one of the qubits will affect the other, allowing the construction of a CNOT logic gate. 一旦这事发生了,即使离子距离很远,操纵其中一个量子位元时还是会影响到另外一个,所以可以做出成功的CNOT逻辑闸。
- CPU which has high performance and low power consumption and cost. LPC2138采用的是ARM7TDMI处理器内核,具有高性能、低功耗、低成本的特点。
- A low power 10 bit/50 MHz pipeline ADC was designed. 介绍了一种50 MHz,10位,5V流水线模数转换器的设计。