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In the designing and exploitation progress of a DSP core,the instruction level simulator can be used in the emulation and debugging,and it is propitious to expedite the rate of development. 在DSP内核的设计、开发过程中,指令级模拟器可用于汇编程序仿真、调试,有利于加快芯片开发进度。
instruction level simulator 指令级模拟程序
instruction level simulation [计] 指令级模拟
Software pipelining is a loop optimization technique used to exploit instruction level parallelism. 摘要软件流水是一种循环程序的优化技术，它可以有效地提高指令级并行性。
Source level debuggers can hide execution details. Step through critical code at the instruction level. 源代码级的调试器可能隐藏运行细节。在指令层级上检查重要的代码。
This paper presents the implementation approach and the experimental results of multimedia realtime processing on the ILP (Instruction Level Parallelism) computing platform. 论了指令级并行运算环境中多媒体数据处理的实现方法和性能。
The design problem of an embedded RISC architecture in parallel processing of algorithm level, instruction level and process level is discussed in this paper. 本文将从算法级并行处理、指令级并行处理与进程级并行处理等三个方面讨论嵌入式RISC体系结构的设计问题.
EPIC defines a new style of architecture that enables higher levels of instruction level parallelism (ILP) without unacceptable hardware complexity. EPIC是一种显性并行指令计算体系结构，主要思想是利用编译器和处理器的协同能力来提高指令级并行度。
The comparison experiments for software pipeline and super block scheduling are done, which shows that the optimization effect can be increased by more than 30% and has obvious relation to instruction level parallelism (ILP). 对编译后端的软件流水和超块调度两种性能优化策略进行对比实验;表明其优化效果在30%25以上;并且代码的指令级并行性(Instruction Level Parallelism;ILP)与优化效果存在明显的相关性.
The concepts of regions in the Instruction Level Parallelism(ILP) and the Explicitly Parallel Instruction Computing(EPIC)are explained. Sevral algorithms of regional scheduling are introduced. 介绍指令级并行性 (IL P)中和指令级计算 (EPIC)中区域的直观概念和这些概念的形式化工作 ,并简单介绍区域的几个调度算法 ,为并行编译中的区域调度问题提供一个系统的、形式化的论述。
At last, the system simulation under different conditions was accomplished by inserting the obtained lumped parameter models into a system level simulator. 将这些物理参数综合在系统仿真器中与外围电路共同进行仿真，准确地评估不同条件下微机械陀螺的行为特性。
The concepts of regions in the Instruction Level Parallelism (ILP) and the Explicitly Parallel Instruction Computing(EPIC)are explained. Sevral algorithms of regional scheduling are introduced. 介绍指令级并行性(ILP)中和指令级计算(EPIC)中区域的直观概念和这些概念的形式化工作,并简单介绍区域的几个调度算法,为并行编译中的区域调度问题提供一个系统的、形式化的论述。
The verification includes RTL simulation, gate level simulation and static timing analysis. 验证工作包括RTL级仿真、门级仿真和静态时序分析。
register transfer level simulator 寄存偏送级模拟程序
Instruction scheduling is used to exploit the instruction level parallelism(ILP)inherent in program through reordering its instructions. 指令调度通过调整指令之间的顺序来提高指令级并行度(ILP)。
English is not the usual medium of instruction in our school. 英语不是我校通常使用的教学语言。
We designed an RTL testbench for asynchronous sampling, an RTL level simulation testbench and a FPGA platform for the chrominance demodulation. 对色度处理算法设计了完整的RTL级仿真平台和FPGA硬件验证平台。
An instruction to go to a subroutine. 一种转移到子程序去的指令。
My reins also instruct me in the night seasons. 我的心肠在夜间也警戒着我。
It is proved by analysis in theory and system level simulation that the adaptive congestion control algorithm can enlarge system throughput while controlling system load. 经过理论分析和系统级仿真，验证了自适应拥塞控制算法在控制系统负载的条件下，提高了系统吞吐量。