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coupled phase locked loop 耦合锁相环
One example is the phase comparator of a phase locked loop. 一个例子是相锁环状态下的相位比较器。
Phase locked loop (PLL) has been widely used in communication system. 锁相环路在通信系统中得到了广泛的应用。
Resolution of Systematic Design Trouble with PLD Interior Phase Lock Loop. 使用PLD内部锁相环解决系统设计难题。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed. 定量分析了数字式锁相倍频器输出信号的相位抖动.
TMS320F240 DSP is used to realize the digital Phase Locked Loop(PLL) and real-ize the hot-swap function of the parallel system. 采用TMS320F240型DSP芯片实现数字锁相同步,实现并联系统的热插拔功能。
This paper discusses a method to demodulate FSK signal, on the basis of FPGA chip, by applying all- digital phase locked loop. 本文研究了一种采用全数字锁相环实现频移键控FSK信号解调的新方案。
The basic principle of using phase locked loop technique to realize the design and analysis of program controlled frequency syntheses was introduced. 本文简要地叙述了应用锁相环路实现信号合成的基本原理。
Abstract：The Phase Lock Loop (PLL) Circuits are widely used in electronic systems especially in receivers. 锁相环路是在现代各种电子系统中，特别是在接收机中应用广泛的一种基本电路。
The coupling visibilities(CV) of temperature sensor heads were measured with phase lock loop technique. 采用锁相环技术测试了各传感器的分光可见度随温度的变化关系。
In this paper the working princi-ple and desiging method of which phase locked loop are discussed the experimental resuIts are given also. 本文分析了无相差锁相环的原理和设计方法，并给出了实验结果。
The transmitter uses a phase locked loop to provide multi-phase clocks for PRBS circuit and 4-to-1 multiplexer to convert parallel data into serial one. 在传输端利用锁相迴路提供多相位时脉输出给乱数产生器和4对1多工器，并将一组并列资料转换为串列输出，再经传输器使输出的资料振幅放大，最后将资料传输至耦合的电极板上。
According to the requirement of controlling the unity power factor rectifier, a novel method , a phase locked loop (PLL), is used to track the phase of fundamental voltage. 针对单位功率因数整流器的控制要求,提出了一种利用锁相环(PLL)来检测基波电压相位,控制整流器交流侧电流与交流侧基波电压同相位的控制策略。
The frequency and phase lock loop has been applied for the carrier recovery of VSB transmission system in high definition TV. 目前，锁频锁相环在高清晰度电视VSB传输系统载波恢复中得到了应用。
Several blocks such as ELST, CRC coder/decoder, Bit synchronousdigital phaselocked loop and jitter attenuate digital phase locked loop aredescribed in detail. 论文对作者所设计实现的部分模块作了较为详细的介绍，包括弹性存储器的设计和CRC编解码的设计以及位同步数字锁相环和抖动衰减锁相环的设计。
The signal processing circuses, including the low-noise pre-amplifier, the filter and the phase lock loop(PLL) demodulation were designed. 分析并研制了系统的信号调理电路，其中包括低噪声前置放大、滤波、锁相环解调。
After the signals treated by a digital phase locked loop of zero phase-difference when phase and frequency following,this problem has satisfactorily been solved. 采用对相位和频率跟踪无相差的数字锁相环对同步信号进行处理可满意地解决上述问题。
To meet the requirements of the target radio frequency (RF) hardware-in-the-loop simulation of the radio detonator, a method using a special phase lock loop (PLL) is presented. 摘要针对某型导弹无线电引信目标射频半实物仿真的需要，提出了一种特殊的环路锁相方法。