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- adder and substracter circuit 加减法电路
- High-speed digit-serial adder and its application. 高速数字串行加法器及其应用。
- Children should be able to add and substract in the third grade. 儿童应该在三年级的时候能够进行加减运算。
- The mean value detector comprises a second adder and a multiplier. 平均值检测电路包括第二加法器和乘法器。
- Lucy knows how to add and substract but fractions have her up a stump. 做加减法，露西不成问题，可分数却难倒了她。
- The paper presents a multiplier circuit based on Booth algorithm when the radix equals four by studying the Booth algorithm. The carry-save-array adder and the pipeline technique are drawn into the design for improving the circuit speed. 通过对 Booth 算法的研究,本文提出了一种基 4 Booth 算法的硬件乘法器电路,为了提高硬件乘法器电路的运算速度,将保留进位加法电路和流水线技术引入了该乘法器电路。
- We have done HSPICE simulation runs of the new style adder, 28-T CMOS full adder and conventional CPL style full adder. 并且通过HSPICE仿真,对28个晶体管的CMOS加法器、传统的CPL加法器和改进型的CPL加法器进行了比较。
- Then, based on this T gate, the 2-5 mixed-valued ten-valued full adder and full subtracter are designed directly by the truth tables. 然后，在此基础上，按真值表直接设计2-5混值／十值全加器和全减器的运算电路。
- Based on the 18-bit floating number representation, the improved multiplier, division, adder and comparator is given, and then the floating arithmetic is completed. 基于18位自定义浮点数格式给出了改进的乘法器、除法器、加法器和比较器,并在此基础上利用已有的算法结构实现了浮点算法。
- Reuses of some adders and registers existing in circuit result in the elimination or minimization of the additional hardware overhead for test. 通过复用部分寄存器和加法器避免或最小化了额外的测试硬件开销。
- I hit him fair and square on the jaw. 我不偏不倚打中他的下巴。
- It is a fact of life and you must face it. 这是严酷的现实，你必须面对它。
- She and I can't live under the same roof. 她和我不能住在一起。
- She had to scrimp and save to pay for her holiday. 她不得不为付假期的费用而苦苦攒钱。
- I'll try and rustle you up something to eat. 我设法给你弄点吃的。
- He sprang up and rushed to the door. 他跳起身，跑到门口。
- He took sick and died a week later. 他得了病，一周后就死去了。
- He's been in and out of prison for years. 他多年来屡次进出监狱。
- The air in the garden was warm and fragrant. 花园里的空气一片温馨。
- The child was tired and fretful. 那孩子又疲倦又烦躁不安。
