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phase lock circuitry 锁相电路
Resolution of Systematic Design Trouble with PLD Interior Phase Lock Loop. 使用PLD内部锁相环解决系统设计难题。
Both incorporation exterior VCO and loop filter could rattling realize celerity Phase Lock function. 结合外部VCO和环路滤波器可以很好的实现快速锁相功能。
Abstract：The Phase Lock Loop (PLL) Circuits are widely used in electronic systems especially in receivers. 锁相环路是在现代各种电子系统中，特别是在接收机中应用广泛的一种基本电路。
The coupling visibilities(CV) of temperature sensor heads were measured with phase lock loop technique. 采用锁相环技术测试了各传感器的分光可见度随温度的变化关系。
This paper presents a digital phase lock technique for UPS inverter output control to meet the trend of UPS digital control. 针对不间断电源(UninterruptedPowerSupply,UPS)控制的数字化趋势,提出了一种应用于数字化UPS的逆变锁相控制技术。
The signals from the REF IN/OUT socket and the SYNC OUT socket can be used to phase lock two instruments where more than 4 channels are required. 信号从参考输入/输出接口和同步输出接口可用于锁相两项文书在4个以上的渠道是必需的。
The frequency and phase lock loop has been applied for the carrier recovery of VSB transmission system in high definition TV. 目前，锁频锁相环在高清晰度电视VSB传输系统载波恢复中得到了应用。
The signal processing circuses, including the low-noise pre-amplifier, the filter and the phase lock loop(PLL) demodulation were designed. 分析并研制了系统的信号调理电路，其中包括低噪声前置放大、滤波、锁相环解调。
Medium Voltage Inverter, Solid State Soft Starter, Pressure Regulation Water Supply System, Synchronously Switchover, phase lock. 关键词:中压变频器,固态软起动器,恒压供水系统,同步切换,锁相技术。
To meet the requirements of the target radio frequency (RF) hardware-in-the-loop simulation of the radio detonator, a method using a special phase lock loop (PLL) is presented. 摘要针对某型导弹无线电引信目标射频半实物仿真的需要，提出了一种特殊的环路锁相方法。
Results show that the phase locking steps occur in the IV-curves. 结果表明，在直流伏安特性曲线上出现了相锁定台阶。
One example is the phase comparator of a phase locked loop. 一个例子是相锁环状态下的相位比较器。
To meet the requirements of the target radio frequency(RF) hardware-in-the-loop simulation of the radio detonator, a method using a special phase lock loop(PLL) is presented. 针对某型导弹无线电引信目标射频半实物仿真的需要,提出了一种特殊的环路锁相方法。
Phase locked loop (PLL) has been widely used in communication system. 锁相环路在通信系统中得到了广泛的应用。
Through the research of direct digital synthesizer (DDS) used as a divider in phase lock loop (PLL), a frequency synthesizer with small frequency resolution ratio and high purity frequency spectrum can be realized. 摘要通过对直接数字合成器在锁相环路中作为分频器应用的研究，使频率合成器可以在实现超细频率分辨率的同时达到高的频谱纯度。
The PLL (phase lock loop) is realized by form of charge pump, its loop filter is passive two-order LPF. Compared to other form of active filter, this CP PLL has less noise, which does some good to its output spectrum. 微波锁相环采用电荷泵的形式,其环路滤波器为无源二阶低通滤波器,相比采用有源滤波器的锁相环,它不会附加有源噪声,而且滤波器结构简单,便于调试。
PLL (phase lock loop) with PFD (phase-frequency detector) have been widely used in recent years.Reason for their popularity include extended tracking range, lower tracking time and low cost. 摘要锁相环(PLL)是一个闭环相位自动控制系统，能够利用一个精确且稳定的频率产生一系列频率准确的信号，为系统内部的其它模块提供稳定的高频时钟。
In order to satisfy the flow measurement precision for big-pipe,multi-paths ultrasonic flow measurement system based FPGA(Field Programmable Gate Array) and phase lock loop(PLL) was developed. 为了满足大管径流量的测量精度,研制了基于现场可编程门阵列器件FPGA和锁相环路的多声路超声波流量测量系统。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed. 定量分析了数字式锁相倍频器输出信号的相位抖动.