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- multiphase clock pulse system 多相时钟脉冲系统
- multiphase clock pulse generator 多相时钟脉冲发生器
- multiphase clock pulse 多相节拍脉冲
- clock pulse system 时钟脉冲系统
- Trigger control circuit from complex programmable logic device (CPLD), ICL7135CN, the clock pulse circuit and optocoupler inverter constituted. 触发控制电路由复杂可编程逻辑器件(CPLD),ICL7135CN,时钟脉冲电路、反相器和光耦构成。
- PULSE system of Bruel & Kjar Company is one of the most extensively used platforms in the field of noise and vibration measurement. Bruel &Kjar公司的PULSE系统是噪声振动测量领域应用最为广泛的系统之一。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时,(或者在最后一个时钟脉冲的下降沿之后)主机将时钟拉低,键盘/鼠标不必重新传输任何数据。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/ mouse does not need to retransmit any data. 如果在第一个高->时钟跳变时,(者在最后一个时钟脉冲的下降沿之后)机将时钟拉低,键盘/标不必重新传输任何数据。
- With the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks can be reduced to be less than 1.2X quantization error theoretically. 理论上,利用所提出之数位校正电路,多相位输出间的相位误差可以减少至1.;2倍量化误差。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the a last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一个高->低时钟跳变时,(或者在最后一个时钟脉冲的下降沿之后)主机将时钟拉低,键盘/鼠标不必重新传输任何数据。
- The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register. 触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟),这取决于移位寄存器的设计。
- A microprocessor designer may decide to make all instructions last five clock pulses. 微处理机设计人员可以决定使所有的指令持续五个时钟脉冲。
- Note that a set of lights attached to O1, O2, O3 would display the numbers of full clock pulses which had been completed, in binary (modulo 8), from the first pulse. 注意,一组接在O1,O2,O3上的灯泡将以二进制(模8)形式显示第一个脉冲以来已完成的完整时钟脉冲数。
- multiphase clock system [计] 多相时钟脉冲系统
- pulse system differential analyzer 脉冲系统微分分析器
- In binary synchronous communication, the use of clock pulses to control synchron ization of data and control characters. 在二进制位同步通信中,使用时钟脉冲来控制数据和控制字符的同步。
- two-phase closed-loop pulse system 二相闭路脉冲系统
- Programmable output clock pulse width 输出脉冲宽度可编程
- To get the current temperature, you must write 35 fixed bytes into the port register.The sensor expects 16 clock pulses on the SCK line while the SS# is low. 为了取得当前温度;你必须写35个固定的字节到端口寄存器.;当ss低的时候,该传感器预计16个时钟脉冲在串行时钟线。
- I suppose you also have a caste system in your society. 我想你们的社会里也有一种等级制度。