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dual shift register 对偶移位寄位器
All nominal outputs of the shift register are 1. 移位寄存器的全部“原”输出都为1。
The parallel number is applied to the shift register. 并行数寄存于移位寄存器。
The logic function of this DET shift register is proved by PSPICE simulation. 该移位寄存器的功能已用PSPICE程序模拟验证。
The shift register should be set or cleared to produce the desired sequence. 移位寄存器应该置位或复位，才能产生所要求的序列。
A DET shift counter designed with the DET shift register is demonstrated. 使用该移位寄存器设计双边沿移位计数器的实例被演示。
Key Words: Primitive trinomials, generalized feedback shift register. 关键词：原生三项式，通用回馈位移暂存器。
DET shift counter designed with the DET shift register is demonstrated. 使用该移位寄存器设计双边沿移位计数器的实例被演示。
The shift register is a device in which information may enter sequentially or in parallel. 移位寄存器是一种能以串行和并行方式输入信息的装置。
In an MOS dynamic shift register the above problem is solved by keeping data in continuous motion. MOS动态移位寄存器的上述问题是通过使输入数据连续不断地循环来解决的。
A shift register that transfers information from stage to stage in response to timing signals. 一种移位寄存器,按定时信号逐级传送信息。
The only difference between the two modes is the way that the shift register is filled. 相似;这两种模式的唯一差别是移位寄存器的填充方式不同。
The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. CMOS移位寄存器和锁存允许与基于微处理器系统直接相连。
If a bit in the cipher text is mangled, one plain text bit is mangled and the shift register is corrupted. 如果密码文本中有一个位出错,则一个纯文本位出错,并且移位寄存器损坏。
This CMOS device includes an input shift register, accompanying data latches, and 16 MOS constant current sink drivers. CMOS器件包含一个输入移位寄存器、随附的数据锁存和16个MOS恒流灌电流驱动器。
This mode uses a shift register that is one block in length and is divided into sections. 该模式使用在长度上为一个块且被分为几部分的移位寄存器。
We also discussed the method of generating security CRC using linear feedback shift register . 在文中我们还讨论了利用线性移位寄存器技术产生安全的CRC校验码的方法。
A monolithic bipolar integrated circuit of ECL high speed 4 bit counter/ shift register is presented. 介绍了一种双极单片高速ECL电路四位计数器／移位寄存器。
To achieve high data rate and low circuit complexity, the architecture combines shift register and tree-type MUX. 为了达到高速传输与低电路复杂性，架构上使用平移暂存器与树状多工器并用的方式。
The twentythree(23) bits residing in the scrambler shift register prior to the transmission of a packet. 传输包之前驻留在编码器移位寄存器中的23比特。