VHDL language is used to describe, define the base pins, add read-write and compile schematics, create the JED files, and download JED files into CPLD to complete the design.

• 并用VHDL语言描述逻辑、定义管脚、增加读写、编译原理图、产生JED文件,将JED文件存入可编程逻辑器件以完成编程设计。