Use fully synchronous design. Asynchronous design is very sensitive to path delay and is therefore not robust. An example of asychronous circuit is the SR latch which uses combinational feedback.

• 使用完全同步设计。异步设计对路径延迟非常敏感,因此不很可靠。异步电路的一个例子是使用组合反馈的SR闭锁。