This thesis proposes a new digital controlled oscillator (DCO) and a new phase frequency detector (PFD) architecture for the all digital phase-locked loop (ADPLL) with low power design.

• 本论文提出一个新的数位控制频率振荡器及一个新的相位频率侦测器之架构以设计一个低功率的全数位式锁相迴路。