This thesis designs a four-stage pipelined Java hardware accelerator. It can execute most of the Java Virtual Machine (JVM), it can run as a single processing unit in an embedded system or FPGA.

• 本文设计了一个具有四段流水线的Java硬件加速器,执行了部分常用的Java虚拟机规范,主要作为单独处理单元运行于嵌入式实时系统或者FPGA。