The gates would have to be stacked on top of a template of CMOS transistors that would relay signals indicating when each gate element should begin and stop processing.

• 这些逻辑闸得叠在设计好的CMOS电晶体板子上，电晶体会给出讯号，告知每个单元闸在什麽时候可以开始或停止处理资讯。