The estimated gates of our proposed architecture in SMIC 0.18 um technology are 15 500 and the estimated frequency of operation is 150 MHz.

• 对该结构使用Verilog HDL语言进行RTL级描述；在SMIC 0.；18 um工艺下综合得到最高工作频率为150 MHz；等效门数是15 500门。