The RTL (Register Transfer Level)design is accomplished by Veirlog hardware description language, and synthesized with the standard cell library of SMIC 0.18um. The working frequency of the adaptive filter is 50MHz.

• 本设计采用Verilog 硬件描述语言完成系统的RTL(Register Transfer Level)级设计；选用SMIC 0.；18um 标准单元库完成逻辑综合；系统工作速度为50MHz。