The PLL is fully integrated onto TSMC 0.25um CMOS process to achieve wide operating frequency, low power and especially low jitter performance.

• 本论文所提出的锁相迴路是用台湾积体电路公司0.；25微米互补式金氧半导体制程设计来达到工作频率范围广，低功率，特别是低相位抖动的特性。