Several clock-pulses with the same frequency and uniform distribution phases are generated by several high-speed buffers in a CPLD chip.

• 为此利用CPLD高速缓冲的延迟特性产生多路同频且相位均匀分布的时钟脉冲，用多个计数器在这两个周期并行计数，用计数结果均值作为最终结果。