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Multiple clock domain 多时钟域
It applies multiple clocks on different pipeline parts basing on their logic complexity, and provides a parallelism on the slow part for throughput compensation. 它允许流水线模块根据各自逻辑复杂度选择不同的工作频率；通过提高简单模块的工作频率，并增加复杂模块的并行度，以实现流水线的指令吞吐率的优化。
The master clock can be asynchronous with PCM data side clock or ADPCM data side clock. Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的，不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的；
During the process of communication between different clock domains,metastability is likely to happen.This paper discusses several applications of different synchronizers in IC asynchronous design. 针对通信过程中多时钟域之间的亚稳态现象,分析了几种同步器在集成电路异步设计中的应用。
The master clock can be asynchronous with PCM data side clock or ADPCM data side clock.Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主时钟与PCM数据端时钟或ADPCM数据端时钟可以是异步的，不同的时钟控制范围内的数据同步或交换是通过一个深度为8的FIFO来实现的；
I didn't wake up until I heard the alarm clock. 直到听到闹钟的铃声我才醒来。
That clock is a family heirloom. 那个座钟是祖传下来的。
I set it by the clock on the railway station. 我是按火车站的大钟对的。
The clock ticks louder and louder in a quiet room. 钟的滴答声在静静的房间里变得越来越响。
The grandfather clock was back in its old place. 落地式大摆钟已放回原处了。
The little clock tinkled out the hours. 那只小钟叮叮当当地报时。
Let's set the clock by the radio time signal. 咱们照着收音机的报时信号把钟对一对。
Closing time at this pub is eleven o' clock. 这酒馆的打烊时间是十一点。
Cross Clock Domain Design and Implementation of Configuration Module in ASIC System ASIC系统中跨时钟域配置模块的设计与实现
Management and design of multiple clocks in FPGA FPGA内的多时钟管理与设计
A clock and two vases stood on the mantelpiece. 壁炉台上摆著一个座钟和两个花瓶。
He is the person with multiple injuries. 他就是那个多处受伤的人。
The clock struck at twelve o'clock sharp. 钟在整十二点钟打点。
At midnight you'll hear the clock strike twelve. 午夜时你会听到钟打12点。
There must be something wrong with my clock. 我的钟一定是坏了。