It also shows that the upper speed limit of iterative cellular array multipliers will be greatly raised by employing the parallel processing technique while the hardware cost remains about the same.

• 设计实例和理论分析都表明:并行处理技术将大大地提高叠接单元阵列乘法器的速度上限,而并行处理乘法器的硬件代价却与改进前相当。