In this thesis we build a model based on a D flip-flop chain and use a statistical method to evaluate the transmission quality of digital logic circuit affected by jitter and skew.

• 本篇论文将以正反器串做为模型，并且利用统计分析的方法，来分析数位电路传输时受到时序抖动以及时脉偏移影响时的传输品质。