In the pursuit of low series resistance in a thin SOI, it is critical to optimize spacer width and utilize fully-silicide S/D.

• 为了让元件在薄的绝缘层上矽的基版上，获得低串联电阻，利用完全镍化矽源/汲极与最佳化间隙壁宽度制程可获取效益。