Here, we use a DLL-based clock generator with nonoverlapping circuit to generate three nonoverlapping phases used for capacitor error-averaging in pipelined ADC.

• 在本论文中，我们利用延迟锁相迴路加上相位非重叠电路来实现一个三相非重叠电路，以供给管线式电容平均容错之类比数位转换器。