Finally, i describe DMA and simulate it with verilog HDL in RTL (Register Transfer Level), which result can satisfy systemic function.

• 并采用Verilog HDL对其进行了RTL级描述,最后根据控制寄存器中START位和SYNC位的不同情况,对DMA整体作了仿真验证工作。 仿真结果表明,该设计能完全满足系统要求。