DDS-driven PLL would alleviate the complexity of the loop design, mid in the mean time obtain a competitive performance compared to traditional analog methods.

• 利用高性能直接数字合成器(DDS)驱动锁相环路，可以在很大程度上降低环路设计的难度，并实现普通模拟方法难以实现的宽带细步进性能。