Compared with a two stage Vdd and Vth voltage assignment with gate sizing algorithm in [13], our algorithm also consume 4.2% and 9.7% less average total power than it.

• 和一个分成两阶段的演算法作比较，我们在中活性与低活性里，也分别可以比他们的演算法减少4.；2%25和9