By taking advantage of the DLL to remove on-chip clock delay, the designer can greatly simplify and improve system level design involving high-fanout, high-performance clocks.
英
美
释义
控制逻辑在反馈时钟到达时采样输入时钟以调整二者之间的偏差,实现输入和输出的零延时。
把海词放在桌面上,查词最方便
触屏版
|
电脑版
©2003 - 2024 海词词典(Dict.cn)
立即下载