Because equivalence checking is designed to check the correctness of automatic synthesis from RTL to netlist, correctness is also the key point, which is concerned in this paper.

• 设计验证系统的初衷是验证给定设计从RTL级到网表级自动综合后电路的正确性，所以综合引擎本身的正确性是本文首要关注的问题。