Always use the global clock buffers on the FPGA to drive internal clock signals. These clock buffers and the associated clock distribution network have been carefully designed to minimize skew.

• 在FPGA上始终使用全局时钟缓冲来驱动内部时钟信号。并且已经仔细设计了这些时钟缓冲和关联时钟配电网,以将畸变减至最小。