A high-speed 16bits*16bits multiplier has been developed, which introduces Modified Booth Arithmetic (MBA), Wallace Tree and 4:2 Compressor, Pseudo 4:2 Compressor and Square Root Carry-Select Adder.

• 根据承担的科研项目的需要实现了高速16bits×16bits的乘法器，采用华东师范大学硕士论文高速可配置基2 FFT处理器的FPGA实现研究了修正布斯编码、华莱士压缩树，4:2压缩器和伪4:2压缩器，平方根求和等新型结构。