A 9-stage pipelined DSP with VLIW architecture is verified by this verification system, and the statement coverage can attain up to 99.9% within 4000 vectors.

• 采用该平台对一个九级流水线的超长指令字结构数字信号处理器进行验证，可以在4000条指令内达到99%25以上的代码语句覆盖率。